Semiconductor circuit manufacturing is subject to certain design rules for laying out features on wafers. As semiconductor circuits become more highly integrated, it is important to design semiconductor chips in such a manner as to provide more elements on a chip for a higher yield in the final product. It is desirable to bring process technology smoothly through development in order to manufacture the product with a competitive yield and efficient die size positioning.
Conventional solutions generally utilize very simple models based on sweeping assumptions about the shape of features on a processed semiconductor wafer. Such models and assumptions result in inaccuracies, leading to less than optimal design rules.
Traditionally, a one-dimensional analysis is used, taking into account critical dimension (CD) tolerances and polysilicon gate levels for making an overlay. Lithographic analysis methods have evolved into two-dimensional shaping techniques that take into account anomalies in simple geometric shapes, such as corner rounding and the like. A simple model of conventional systems may assume all contacts drawn at the same square dimension S×S translate to circular features on the wafer with a nominal radius, e.g., r, with a normal Δr distribution around 0, with sigma of 5 nm. 90° sharp corners as drawn, result in rounded corners on wafer, with the simple model treating this as a semicircular arc. Errors associated with using simplistic shapes can be a few to tens of nm. This is an appreciable fraction of the target CD in semiconductor technology that involves sub-100 nm dimensions.
Thus, to obtain even higher yields and more optimal die pattern edge positioning and mask design, there is a need for a more sophisticated approach to the design process. More advanced modeling and predictive software is required to calculate accurate metrics for more complex feature shapes than the simple geometric shapes currently analyzed, thereby to obtain a truer representation of actual manufactured shapes of the semiconductor chip features.